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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Features
* Class 2 and 3 (up to 10 meter range) compliant with Bluetooth Specification 1.1 * Fully integrated single-chip transceiver with onchip PLL, VCO, LNA, up/down converter, and digital GFSK modem * Seamless interface to BlueRF RXMODE2 with unidirectional / JTAG serial interface or bidirectional / DBUS serial interface * Up to -90dBm receiver sensitivity * Superior adjacent channel selectivity of -6 at 1MHz offset * Support dual reference clock frequency: 13/16MHz * Bluetooth BQB QPL qualified - ID = B00992
General Descriptions
The PT8R1002 is a part of the PTI Bluetooth product family. It is a short-range microwave-frequency radio transceiver for Bluetooth links that operates in the 2.4 GHz to 2.5 GHz ISM band. The device consists of a fully integrated 2.4 GHz radio transceiver with GFSK modem. This radio IC is based on PTI's proprietary radio architecture employing direct conversion scheme, which offers superior channel selectivity, and is implemented in CMOS technology, which provides low cost integrated RF and baseband solutions for Bluetooth applications. The PT8R1002 incorporates the complete receive and transmit components including PLL, VCO, LNA, up/ down converter, channel select filters, and digital GFSK modem.
Application
* ISM 2.4GHz wireless systems * Mobile phones and Handset
Block Diagram
XTALIN
Clock Generator
Reference divier
PFD
XTALOUT DATACLK
Loop Filter Prescaler
LO generation
Frequency Synthesizer
DA GFSK Modulator
TXDATA TXDATA_EN
v VGA
DA
VGA
PA
RF_OUT
MDSEL TXACTIVE RXACTIVE TCL TMS TDI TDO SYNCDETECT RESET
GFSK Demodulator AD VGA v DA
PA_CNT
RF control
Fast DC Cancellation
Automatic Filter Calibration
RF power measure
Gain Control LNA RF_IN
RXDATA
AD
VGA
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Pin Information
Pin Configuration
V CO_V CC 32
40
39
38
37
36
35
34
33
31
AN_VCC AN_VCC TEST_P1 TEST_P2 TEST_P3 TEST_P4 TEST_P5 DIG_VCC TXACTIVE RXACTIVE
1 2 3 4 5 6 7 8 9 10 11 RX D AT A 12 TXDATA 13 TXDATA_ EN 14 DATACLK 15 IO_ V CC 16 R ESET 17 TCK 18 TDO 19 TDI 20 TMS
V CO_V CC
RF _V C C
PA_ C NT
RF_V C C
RF_OUT
MDSEL
RF_I N
NC
NC
30 29 28 27
TEST_P6 N/C N/C VCO_VCC VCO_VCC AN_VCC AN_VCC XTALIN XTALOUT SYNCDETECT
PT8R1002
(40pin 6mm X 6mm QFN)
26 25 24 23 22 21
Ordering Information
Pa r t Numbe r R e pr e s e nt a t ion De vice Compone nt s Pa ck ing Lot Tr a ve le r Tray Normal T&R Q F N 40 Tray Pb(Lead) Free T&R
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L a be l PT8R1002ZB PT8R1002ZBX PT8R1002ZBE PT8R1002ZBXE
M a r k ing PT8R1002ZB PT8R1002ZB PT8R1002ZBE PT8R1002ZBE
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PT8R1002ZB PT8R1002ZBX PT8R1002ZBE PT8R1002ZBXE
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Pin Description
P in No 1, 2, 24, 25 3, 4 5, 6, 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 26, 27, 31, 32 28, 29, 35, 36 30 33, 38 34 37 39 40 P in Na me
AN_VCC TEST_P1, TEST_P2 TEST_P3 TEST_P5 DIG_VCC TXACTIVE RXACTIVE RXDATA TXDATA TXDATA_EN DATACLK IO_VCC RESET TCK TDO TDI TMS SYNCDETECT XTALOUT XTALIN VCO_VCC
Typ e
Power
Descr ip t ion Power supply for analog baseband core (2.7V) serial data, test purpose only (see note3) serial data, test purpose only (see note3) supply for digital core (2.7V) transmitter enable, active high receiver enable, active high serial data, receive data serial data, transmit data active high, timing reference of valid data clock, 13/16MHz reference data clock supply for digital I/O (3.3V) active low, reset signal for internal registers clock, a serial register interface clock serial data, Phy control register serial data output serial data, Phy control register serial data input serial data, control signal of Phy's TAP controller active high, indication of SYNC word detection clock, reference crystal output (see note2) clock, reference crystal input (see note2) supply for PLL block (2.7V) No connection analog, test purpose only (see note3) supply for RF block (2.7V) analog, 2.4GHz transmitted signal from internal PA analog, 2.4GHz received signal from antenna analog, power control to external power amplifier select data, BlueRFTM directional mode selection pin (see note1)
DO/AO DO Power DI DI DO DB DI DO Power DI DI DB DI DI DI AO AI Power
NC TEST_P6 RF_VCC RF_OUT RF_IN PA_CNT MDSEL
AO Power AO AI AO DI
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Note : 1. The pin indicates the directional mode of BlueRFTM RXMODE2.
Pin Name MDSEL TXACTIVE RXACTIVE TXDATA_EN TXDATA I/O DI DI DI DI DB Type select data active high active high active high serial data BlueRFTM RXMODE2 BlueRF RXMODE2 LOW Don' t use Don' t use Don' t use BTXD Transmit (DI), Receiver (DO) RXDATA SYNCDETECT DATACLK RESET TCK TMS TDI TDO DO DI DO DI DI DI DI DB serial data active high clock active low SPI clock control data serial data serial data Don' t use BPKTCTL BRCLK BnPWR BDCLK BnDEN Don' t use BDDATA Write (DI), Read (DO) BTXD (DI) BRXD BPKTCTL BRCLK BnPWR BDCLK BnDEN BMISO BMOSI (DO) Bidirectional interface Unidirectional interface HIGH BTXEN BRXEN BPAEN
2. The default supporting reference clock is 13MHz. To use 16MHz as reference clock, it is necessary to program the RF register through serial interface at the initial stage. The register description should be referred for the change. 3. These pins should be open in normal operation.
Functional Description
Bluetooth is an open specification for short-range data communications. It operates in the globally available 2.4 GHz to 2.5 GHz ISM free band and uses fast frequency hopping (1600 hop/s) over 79 available channels (2.402 to 2.480 GHz) with a maximum data rate of 1 Mbit/s. The PT8R1002 is intended for the use in 2.4GHz ISM frequency band wireless systems, especially, Bluetooth. The transceiver consists of a fully integrated 2.4 GHz radio transceiver, frequency-hopping synthesizer, and analog-to-digital and digital-to-analog converters for the baseband interface. As illustrated in Figure 1, the radio module requires only an external antenna, antenna switch and crystal to complete the analog front end.
RF receiver
The receiver front-end converts the incoming RF signal in 2.4GHz ISM frequency band to a digitized signal for digital signal processing. The receiver is composed of a LNA, a complex RF-to-Baseband down conversion Mixer, an AGC/complex filter, a dual ADC for the I/Q signal paths, and phase locked loop synthesized local oscillator. The first stage is a single-ended LNA with external matching circuit. The LNA is followed by quadrature down conversion mixers. The down conversion mixer employs PTI' s proprietary technologies to minimize RF coupling and DC offsets.
Channel selection filter and AGC
With the use of direct down-conversion scheme, the complex baseband filters carry out excellent channel selection and image-free operations. As a result, the receiver exceeds the Bluetooth 1.1 requirements for adjacent channel & image rejection and provides superior performances in the presence of ISM-band RF interferers.
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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The AGC and filter are optimally designed to meet both the stringent requirements of gain setting and Adjacent Channel Selectivity (ACS) in Bluetooth. In ISM frequency band applications, excellent adjacent channel selectivity is required, because there can be too many blockers operating simultaneously. Thus, both channel filter and AGC circuits must have high linearity and low noise performance. The first channel filter and first AGC used have IIP3 greater than 30dBm. The remaining channel filters and AGC' s are optimized to obtain high ACS.
PT8R1002 supports the BlueRFTM RXMODE2 Bluetooth interface with both unidirectional and JTAG serial interface or bidirectional and DBUS serial interface which are all compatible with the PTI PT8R1202 Bluetooth Baseband controller. In this mode, external Bluetooth baseband delivers the SYNCWORD detection indication to PT8R1002 when it detects a Bluetooth SYNCWORD in received data.
I/O Description
RF interface
RF transmitter
The transmitter is composed of a dual DAC for the I/Q signal paths, channel filter, Baseband-to-RF up- conversion Mixer, and power amplifier with 2 dBm output power. The phase locked loop frequency synthesizer is shared with RF receiver to minimize the hardware components. The transmitter features a direct up-conversion scheme to minimize the frequency drift during a transmit timeslot and also results in a well-controlled modulation index. The baseband channel filter offers excellent out-of-band suppression and equalized signals to minimize the interference with the on-chip receiver. With the nominal transmit power of 0 dBm, the transmitter can be used in class 2 and class 3 radios, and can be simply implemented in class 1 with an external RF power amplifier. The radio interface establishes the connection of antenna-toLNA in receiving mode and antenna-to-power amplifier in transmitting mode. The actual configuration of RF front-end can be seen Figure 1. An antenna filter is located between the antenna and SPDT (Single Pole Double Throw) switch. The antenna filter blocks unwanted signals in receive mode and suppresses harmonics in the transmit mode. The filter can be either a discrete component or fully integrated in ceramic substrate. The SPDT switch isolates the transmit path and the receive path and thus impedance can be matched for entire signal path. A matching circuit is placed between LNA_IN pin and SPDT switch to match the 50 ohm source to the complex input impedance of the LNA. Another external matching circuit is required at PA_OUT to transfer maximum power to the antenna. BlueRF RXMODE2 baseband interface PT8R1002 supports the BlueRFTM RXMODE2 Bluetooth radio interface with unidirectional and JTAG serial programming interfaces or bidirectional and DBUS serial programming interface, which are compatible with the PTI PT12002 Bluetooth baseband controller. In RXMODE2, the SYNCWORD correlator is located in baseband controller, and it detects signal feeds into PT8R1002. Unidirectional interface The interface connections for unidirectional mode are shown in Figure 4.
PLL
The radio synthesizer is fully integrated and thus does not require any external elements. It is designed with PTI' s proprietary frequency synthesizer technologies, which minimize phase noise and coupling to the RF amplifiers. An on-chip reference oscillator is provided and requires an external crystal or a reference clock. The external crystal (reference clock) frequency should be 13MHz or 16MHz with 20 ppm accuracy.
Baseband modem
The baseband GFSK modem is implemented in a compact dedicated logic that provides excellent performance in the presence of noise, interferers, and frequency offset/drift, while consuming very small power. The baseband modem interface is designed to transfer Bluetooth data between PT8R1002 and a baseband controller. The GFSK demodulator performs frequency demodulation. The inherent frequency offset compensation block can guarantee stable operation in the present of large frequency deviation, which is activated with SYNCDETECT asserted. The GFSK modulator provides a precise modulation index control and a Gaussian spectral shaping.
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Figure 4. BlueRF RXMOD2 Unidirectional baseband interface
BRXEN BTXEN BPKTCTL BSEN BXTLEN BTXD BPAEN BnPWR BRCLK
and data extraction Correlator
BRXD
RXDATA(GPA4) RXACTIVE(GPA1) TXACTIVE(GPA0) SYNCDETECT(GPA5) GPD4(optional) GPD5(optional) TXDATA(GPA3) TXDATA_EN(GPA2) RFRESET(GPA7) DATACLK(GPA6)
Fr equency offset canc ellation
Demodulation
Bluetooth Radio Transceiver Baseband Interface
Register Control I/F
BDCLK BnDEN BMOSI BMISO
BLUERF_TCK(GPA8) BLUERF_TMS(GPA9) BLUERF_TDI(GPA10) BLUERF_TDO(GPA11)
(Unidirectional, JTAG SPI)
The unidirectional mode allows the PT8R1002 to be controlled with minimum reference to the previous state of the interface. This allows the state of PT8R1002 to be inferred by examining the logic levels on the interface signals. The unidirectional interface can be split into two subsections: RF data and control path, register control interface. In BlueRF interface, ten signals are used in the RF data and control path, and four in the register control interface. All of the signals are unidirectional. However, the BSEN (Hop frequency synthesizer enable) and BXTLEN (a strobe which enables the RF oscillator) are not supported as explicit signal in the PT8R1002. Instead, these equivalents functions can be supported using serial programming through JTAG interface. The unidirectional interface requires that the PT8R1002 control registers interface to the Baseband via an IEEE 1149.1 JTAG interface. The unidirectional interface requires that the Baseband portion of the interface is referenced to a Baseband generated clock.
Bidirectional interface The bidirectional mode provides the lowest pin count interface between the baseband and RF piece. The interface connections for bidirectional mode are shown as follows: As similar to unidirectional interface, the bidirectional interface can be split into two subsections: RF data and control path, register control interface. The bidirectional interface uses a DBus control register interface. In BlueRF interface, five signals are used in the RF data and control path, and three in the register control interface. There are two bidirectional signals such as BTXD and BDDATA. The direction of the two bidirectional pads (BTXD, BDDATA) is controlled by separate state machine in the baseband and PT8R1002. The baseband state machine is the master and controls the state machine in the PT8R1002 in an open loop manner. To prevent bidirectional data contention, baseband must ensure not to occur during reset and normal operation.
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Figure 5. BlueRF RXMOD2 Bidirectional baseband interface
Fr equency offset cancellation
Demodula tion
BPKTCTL BXTLEN BTXD BnPWR BRCLK
SYNCDETECT(GPA5) GPD5(optional) TXDATA(GPA3) RFRESET(GPA7) DATACLK(GPA6)
and data extracti on Correlator
Bluetooth Radio Transceiver Baseband Interface (Bidirectional, DBUS SPI)
Register Control I/F
BDCLK BnDEN BDDATA
BLUERF_TCK(GPA8) BLUERF_TMS(GPA9) BLUERF_TDO(GPA11)
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Transmit operation in Unidirectional interface The primary signal for data transmit is TXACTIVE signal. The actual data transmission starts after TXDATA_EN provided by baseband. During transmit mode, DATACLK is sent from PT8R1002 to baseband as a timing reference. The baseband circuit transmits data to the PT8R1002 at the falling edge of DATACLK, whereas the PT8R1002 latches the data at the rising edge of DATACLK. The state of PT8R1002 transitions from the idle state when the baseband drives TXACTIVE HIGH. TXACTIVE enables all the transmit circuitry except for the final output stage. TXACTIVE is driven high at a time TTuningTX
before the hop frequency synthesizer has settled to allow any frequency offsets caused by the TX circuitry to be eliminated. Either when, or just before, the TX circuitry has correctly settled on frequency, the baseband drives TXDATA_EN HIGH, which enables the PA stage, and causes the unidirectional interface to enter the transmit data state. The baseband drives data to the PT8R1002 on the falling edge of DATACLK, and the PT8R1002 reads the transmit data on the rising edge. When all the data has been transmitted, the baseband drives TXDATA_EN and TXACTIVE LOW to disable the PA stage and return to the idle state.
Figure 6. Transmit procedure timing diagram in unidirectional interface
Idle
JTAG Programming HOP CMD TXACTIVE TXDATA_EN TXDATA RXACTIVE SYNCDETECT RXDATA DATACLK
VCO Tuning
Tx-Ramp-Up
Tx-Burst
Tx-Ramp-Down
Idle
Tx DATA
tTuningTX
tRamp-Up
tRamp-Down
Figure 7. Transmit signal timing diagram in unidirectional interface
DATACLK(13MHz,O) TXACTIVE(I) TXDATA_EN(I) TXDATA(I) RXACTIVE(I) SYNCDETECT(I) RXDATA(O) PE PE SYNC WORD SYNC WORD TE HEDER+PAYLOAD
tRamp-Up
PE : Preamble TE : Trailer
tRamp-Down
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Transmit operation in Bidirectional interface Unlike unidirectional interface, the primary procedure for data transmit is to activate internal TXACTIVE signal by writing HIGH to TXA field of BT_RF_PLL_CTRL1 through DBUS interface. The actual transmission starts after HIGH value of SYNCDETECT provided by baseband. During transmit mode, DATACLK is sent from PT8R1002 to baseband as a timing reference. The baseband circuit transmits data to the PT8R1002 at the falling edge of DATACLK, where the PT8R1002 latches the data at the rising edge of DATACLK. The PT8R1002 transitions from the idle state when the baseband writes HIGH to TXA field of BT_RF_PLL_CTRL1 through DBUS interface.
Updating HIGH to that field enables all the transmit circuitry except for the final output stage. DBUS writing is executed at a time TTuningTX before the hop frequency synthesizer has settled to allow any frequency offsets caused by the TX circuitry to be eliminated. Either when, or just before, the TX circuitry has correctly settled on frequency, the baseband drives SYNCDETCT HIGH, which enables the PA stage, and causes the bidirectional interface to enter the transmit data state. The baseband drives data to the PT8R1002 on the falling edge of DATACLK, and the PT8R1002 reads the transmit data on the rising edge. When all the data has been transmitted, baseband should write LOW to TXA field of BT_RF_PLL_CTRL1 to disable the PA stage and return to the idle state.
Figure 8. Transmit signal timing diagram in bidirectional interface
Idle
DBUS Programming HOP CMD SYNCDETECT TXDATA
VCO Tuning
Tx-Ramp-Up
Tx-Burst
Tx-Ramp-Down
Idle
TXACTIVE On CMD
TXACTIVE Off CMD
Tx DATA
DATACLK
tTuningTX
tRamp-Up
tRamp-Down
Figure 9. Transmit signal timing diagram in bidirectional interface
TXACTIVE Off CMD write
DATACLK(13MHz,O) DSUB SPI SYNCDETECT(I) TXDATA(I)
TXACTIVE On CMD write
PE
SYNC WORD HEDER+PAYLOAD
PE SYNC WORD TE
tRamp-Up
PE : Preamble TE : Trailer
tRamp-Down
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Receive operation in Unidirectional interface The primary signal for data reception is RXACTIVE signal. When RXACTIVE goes to high, the RF circuitry starts to operate and send data after fixed time from RXACTIVE. The baseband receives data and searches for the access code. During receive mode, DATACLK is sent from PT8R1002 to baseband as a timing reference. The PT8R1002 circuit sends the data to baseband at the rising edge of DATACLK, where the baseband latches the data at the falling edge of DATACLK. Prior to receiving information over air, the baseband transfers control information including the hop frequency over the JTAG interfaces, and enters PT8R1002 into search access code state after fixed time to turn on receiver circuitry by driving
RXACTIVE HIGH. In the search access code state, the baseband performs all of the tasks required to correlate with the access code from the receive data. When the baseband has correlated the access code, then it drives SYNCDETECT HIGH and makes PT8R1002 enter into receive payload state. During the payload, PT8R1002 eliminates any frequency offset between local and remote Bluetooth devices based on its measurement during syncword acquisition. PT8R1002 transmits demodulated data to the baseband at half frequency of DATACLK, which can be read by the baseband using appropriate timing recovery algorithm. The unidirectional interface is returns to the idle state with the baseband driving RXACTIVE LOW after a fixed interval of TRxOff.
Figure 10. Receiver procedure timing-diagram in unidirectional interface
Search Access Code
Idle
JTAG Programming HOP CMD TXACTIVE TXDATA_EN TXDATA RXACTIVE SYNCDETECT RXDATA DATACLK
VCO Tuning
Rx-On
Rx-Burst
Idle
Valid Rx Data
tTuningRX
tRxOn
tAccessCode
tRxOff
Figure 11. Receiver signal timing diagram in unidirectional interface
DATACLK(13MHz,O) TXACTIVE(I) TXDATA_EN(I) TXDATA(I) RXACTIVE(I) SYNCDETECT(I) RXDATA(O)
tRxOn
PE SYNC WORD TE
tRxOff
HEADER+PAYLOAD
PE : Preamble TE : Trailer
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Receive operation in Bidirectional interface Unlikely unidirectional interface, the primary procedure for data reception is to activate internal RXACTIVE signal by writing HIGH to RXA field of BT_RF_PLL_CTRL1 through DBUS interface. The RF circuitry starts to operate and send data after fixed time from writing data to the field. Right after writing HIGH to the field, the directional of bus is changed and PT8R1002 starts to drive TXDATA. Therefore, the baseband should disable the bus driving before the completion of register writing in order to prevent bus contention. Then, the baseband receives data and searches for the access code. During receive mode, DATACLK is sent from PT8R1002 to baseband as a timing reference. The PT8R1002 circuit sends the data to baseband at the rising edge of DATACLK, where the baseband latches the data at the falling edge of DATACLK. Prior to receiving information over air, the baseband transfers
control information including the hop frequency over the DBUS interfaces, and enters PT8R1002 into search access code state after fixed time to turn on receiver circuitry by writing HIGH to RXA field of BT_RF_PLL_CTRL1. In the search access code state, the baseband performs all of the tasks required to correlate with the access code from the receive data. When the baseband has correlated the access code, then it drives SYNCDETECT HIGH and makes PT8R1002 enter into receive payload state. The bidirectional interface returns to the idle state by the baseband writing LOW to RXA field of BT_RF_PLL_CTRL1 to turn off RX circuitry after fixed TRxOff. Right after writing LOW to the field, the directional of bus is changed and PT8R1002 disable to drive TXDATA. At that time, the baseband should enable the bus driving after the completion of register writing in order to prevent bus floating. Power-up sequence
Figure 12. Receiver procedure timing-diagram in bidirectional interface
Search Access Code RxIdle
Idle
DBUS Programming HOP CMD SYNCDETECT TXDATA
VCO Tuning
Rx-On
Rx-Burst
Idle
RXACTIVE On CMD
RXACTIVE Off CMD
Valid Rx Data
In Direction
DATACLK
Output Direction
In Direction
tTuningRX
tRxOn
tAccessCode
tRxOff
Figure 13. Receiver signal timing diagram in bidirectional interface
RXACTIVE Off CMD write
DATA_CLK(13MHz,O) DSUB SPI SYNCDETECT(I) TXDATA(I/O)
RXACTIVE On CMD write
tRxOn
PE SYNC WORD TE
tRxOff
HEADER+PAYLOAD
PE : Preamble TE : Trailer
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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The power-up sequence of PT8R1002 is very simple mechanism. After power is applied to the PT8R1002, the activating RESET signal into LOW for tRESET is the only required operation. After this procedure, PT8R1002 will come into idle mode for waiting transmit or receive operation indicated by Bluetooth baseband. Before this normal operation, all SPI register value should be initialized even though its value is set by the default value. The initialized value will be provided by PTI. After activating RESET signal, 13 or 16MHz baseband reference signal, DATACLK will be activated until execution of external power down command through SPI interface. Figure 14. Power-up sequence procedure timing-diagram
Power-off
RESET
Idle
VCO Tuning
Rx-On
Power-down sequence
POWER RESET Serial Programming SPI initialization for all registers TXACTIVE TXDATA_EN TXDATA RXACTIVE SYNCDETECT RXDATA DATACLK HOP CMD
Search Access Code
Receiver Operation
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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The lowest operation power state of PT8R1002 is Sleep state, where all clocks including RF and baseband and circuits in the PT8R1002 is placed in their minimum power mode. In this mode, the control register can be accessed through serial interface logic and retain their programmed value. To enter into Sleep state, power-down command which sets power-down of clock generator including crystal buffer should be programmed through the serial interface. After power-down command, the DATACLK from the PT8R1002 will stop until it comes back to Idle state. To escape from Sleep state, power-up command which sets powerup of clock generator should be programmed through the serial interface. After power-up command, the DATACLK will start again from the PT8R1002 into external baseband. Figure 15. Power-down sequence procedure timing-diagram
Idle
POWER RESET JTAG Programming Power Down CMD TXACTIVE TXDATA_EN TXDATA RXACTIVE SYNCDETECT RXDATA DATACLK
Sleep
Idle
VCO Tuning Tx-Ramp-Up
Power Up CMD
HOP CMD
Transmit Operation
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Power control In the PT8R1002, there are five different states with different current consumption; Sleep, Idle, VCO active, TX active, and RX active. Upon reset, the PT8R1002 stays in the Idle state to wait for the command through serial programming interface from the baseband controller. In the Idle state, there is DATACLK from the radio to the baseband controller. In the Idle mode, all RF circuits are shut down to reduce the static current consumption. Only the reference clock oscillator and DATACLK pump to the baseband is active. After HOP set command through the serial programming, the VCO will operate to lock the programmed channel frequency. Owing to the signal such as RXACTIVE or TXACTIVE, the PT8R1002 will enter into the active state such as TX active state and RX active state. In Figure 16. State transition diagram for power control
those state, all RF circuits and GFSK modem will operate and result in the maximum current consumption. In the unidirectional mode, the falling signal of RXACTIVE or TXACTIVE will make the PT8R1002 into Idle state automatically. In the bidirectional mode, the explicit command to stop receive or transmission through serial programming will make the PT8R1002 into Idle state. The PT8R1002 enters into Sleep state by power down command through serial programming. Sleep state is the least power consumption among other states and all clocks include reference oscillator will stop the operation as well as the power down of all RF circuits. In Sleep state, only the serial programming interface logic can operate which uses clock from external device. However, the value of all registers will sustain until the wake up from Sleep state. Following figure shows the state transition in terms of power control.
RX active state (IRX)
Receive command
TX active state (ITX)
Transmit command RXACTIVE off
VCO active state (IVCO)
HOP command
TXACTIVE off
Idle state (IIdle)
Power-Down command Power-Up command
Sleep state (ISleep)
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Timing parameter Parameter
tTuningTX, tTuningRX tRamp-Up
Min
80usec 30usec
Max
90usec 40usec
Comment
Time for PLL to lock to desired frequency Time from TXACTIVE activating point to TXACTIVE_EN activating point in unidirectional interface Time from TXACTIVE on command writing point to SYNCDETECT activating point in bidirectional interface Time from TXACTIVE_EN deactivating point to TXACTIVE activating point in unidirectional interface Time from SYNCDETECT deactivating point to TXACTIVE off command writing point in bidirectional interface Time from RXACTIVE activating point to received data sending point to the baseband in unidirectional interface Time from RXACTIVE on command writing point to received data sending point to the baseband in bidirectional interface Time from SYNCDETECT deactivating point to RX circuitry turn off point Time for minimum pulse width of RESET
tRamp-Down
3usec
5usec
t RxOn
110usec
130usec
tRxOff tRESET
3usec 100nsec
5usec -
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Serial Programming Interface (JTAG interface) The serial programming interface is a JTAG boundary-scan architecture compliant with IEEE 1149.1. Interconnection between the serial interface and external baseband consists of four 1-bit digital signals : control data input(TDI), control mode select (TMS), control clock (TCK) and control data output (TDO). You must refer to the full IEE std 1149.1-1990 Standard Test Access Port and Boundary-Scan Architecture document for a complete, definitive description of the operation of the fundamentals of the JTAG interface. PT8R1002 support TCK up to 13MHz. Table 1. TAP instructions
Instruction EXTEST Opcode 0x000000 Description EXTEST initiates testing of external circuitry, typically board-level interconnects and off chip circuitry. EXTEST connects the Boundary-Scan register between TDI and TDO in the SHIFT_DR state only. When EXTEXT is selected, all output signal pin values are driven by values shifted into the Boundary-Scan register and may change only on the falling-edge of TCK in the Update_DR state. Also, when EXTEST is selected, all system input pin states must be loaded into the Boundary-Scan register on the rising-edge of TCK in the Capture_DR state. Values shifted into input latches in the Boundary-Scan register are never used by the processor's internal logic. SAMPLE / PRELOAD performs two functions: * When the TAP controller is in the Capture-DR state, the SAMPLE instruction occurs on the rising edge of TCK and provides a snapshot of the component's normal operation without interfering with that normal operation. The instruction causes Boundary-Scan register cells associated with outputs to SAMPLE the value being driven by or to the processor. * When the TAP controller is in the Update-DR state, the PRELOAD instruction occurs on the falling edge of TCK. This instruction causes the transfer of data held in the Boundary-Scan cells to the slave register cells. Typically the slave-latched data is then applied to the system outputs by means of the EXTEST instruction. IDCODE is used in conjunction with the device identification register. It connects the identification register between TDI and TDO in the Shift_DR state. When selected, IDCODE parallel-loads the hard-wired identification code (32 bits) on TDO into the identification register on the rising edge of TCK in the Capture_DR state. NOTE: The device identification register is not altered by data being shifted in on TDI.
SAMPLE / PRELOAD 0x000001
IDCODE
0x011111
REGISTER PROGRAMMING
BYPASS
0x1SSSSS REGISTER PROGRAMMING instruction select the REGISTER with address indicator SSSSS. * When the TAP controller is in the Capture-DR state, the REGISTER PROGRAMMING instruction occurs on the rising edge of TCK and executes a snapshot of register addressed SSSSS into serial register. * When the TAP controller is in the Update-DR state, the REGISTER PROGRAMMING instruction occurs on the falling edge of TCK. This instruction causes the transfer of data held in serial register to register addressed SSSSS. 0x111111 BYPASS instruction selects the Bypass register between TDI and TDO pins while in SHIFT_DR state, effectively bypassing the processor's test logic. 0 is captured in the CAPTURE_DR state. While this instruction is in effect, all other test data registers have no effect on the operation of the system. Test data registers with both test and system functionality perform their system functions when this instruction is selected.
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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SPI Registers Map The values of all registers except read-only are set by default values after rest. The default values can be overrided by accessing each register. Typical register values are subject to change and should be obtained from PTI. During normal operation, SPI access should occur to address the following functions only. Programming PLL hop frequency of BT_RF_PLL_CTRL0 Setting Tx power control value of BT_RF_TX_CTRL in the transmit mode Reading receive signal strength indication of BT_RSSI_STA in the receive mode Programming TXA or RXA of BT_RF_PLL_CTRL1 to indicate transmit or receive mode in bidirectional interface Table 2. SPI register address map
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17~0x1D 0x1E 0x1F Name BT_SOFT_RESET BT_MODEM_CTRL BT_RF_RX_CTRL BT_RF_TX_CTRL BT_RF_BB_CTRL0 BT_RF_BB_CTRL1 BT_RF_PLL_CTRL0 BT_RF_PLL_CTRL1 BT_RF_PLL_CTRL2 BT_RF_PLL_CTRL3 BT_RF_TIM_CTRL0 BT_RF_TIM_CTRL1 BT_RF_TIM_CTRL2 BT_RF_TIM_CTRL3 BT_RF_TIM_CTRL4 BT_RF_TIM_CTRL5 BT_RF_AUX_CTRL0 BT_RF_AUX_CTRL1 BT_RSSI_STA BT_RF_STA BT_DAC_TEST_CTRL BT_PWD_CTRL0 BT_PWD_CTRL1 BT_PWDN IDCODE Attribute write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read read read/write read/write read/write write read Description RESET by serial interface* Modem control register RF receiver control register RF transmitter control register RF baseband control0 register RF baseband control1 register RF PLL control0 register RF PLL control1 register RF PLL control2 register RF PLL control3 register RF timing adjustment configuration0 register RF timing adjustment configuration1 register RF timing adjustment configuration2 register RF timing adjustment configuration3 register RF timing adjustment configuration4 register RF timing adjustment configuration5 register RF auxiliary control0 register RF auxiliary control1 register Modem RSSI register RF status register DAC test register MODEM power detector register0 MODEM power detector register1 Reserved Power down register IDCODE
* Equivalent to hardware reset by asserting RESET pin.
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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* The values in all registers are the recommended initial value to be set by the serial programming interface, since some of them may be different value with the default configuration by hardware after reset. Also, these value can be changed in order to be optimized for special purpose. Please contact PTI semiconductor to get up-to-date configuration.
0x01 15 CKS 0 TEPM BT_MODEM_CTRL 13 12 11 01011b
14
10
9
8
7
6
5 0
4 1
3 1
2 1
1 TEPM 00b
0
CKS
0111b External power amp drive enable mode 00 : off 01 : on 10/11 : on during TXACTIVE is high Reference clock select flag 0 : 13MHz 1 : 16MHz
0x02 15 01b 0x03 15
14
BT_RF_RX_CTL 13 12 11 0 01b
10
9 1000b
8
7
6 0b
5
4
3 2 000000b
1
0
14
OS
TPG TAG
BT_RF_TX_CTL 13 12 11 10 9 8 7 6 5 OS TPG 1 0 0111b 11111b Output DATACLK PAD strength 0 : The driving capability of DATACLK is low 1 : The driving capability of DATACLK is high External power amp gain control 00000b (1mA) ~ 11111b(0mA) with 32uA step Transmission AGC gain control 000b(-3dB), 001b(-1.5dB), 010b(0dB), 011b(1.5dB), 100b(3dB), 101b(4.5dB), 110(6dB), 111(7.5dB) BT_RF_BB_CTRL0 13 12 11 0 0 1 BT_RF_BB_CTRL1 13 12 11 1010b
4
3
2
1 TAG 001b
0
0x04 15
14 0
10 1
9 0
8 1
7 11b
6
5 0
4
3 0011b
2
1
0 0
0x05 15 0
14
10 0
9
8 111b
7
6
5 011b
4
3
2 0000b
1
0
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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0x06 15 TXA 0
BT_RF_PLL_CTRL0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXA TG CH 0 0111111b 0000000b TXA Internal TXACTIVE signal generation in bidirectional interface. Writing HIGH For more detail operation, refer to I/O description of transmit operation. This field does not affect in unidirectional interface. RXA Internal RXACTIVE signal generation in bidirectional interface. For more detail operation, refer to I/O description of receiver operation. This field does not affect in unidirectional interface. TG[6] Internal pre power amp gain control with bias change 1 : gain increase, 0 : gain decrease TG[5:0] Internal pre power amp gain control with driving ability 000000b(minimum gain) ~ 111111b(maximum gain) CH Frequency channel selection 0000000b : 0 channel(2402MHz), 0000001b : 1 channel(2403MHz), ... BT_RF_PLL_CTRL1 13 12 11 0 BT_RF_PLL_CTRL2 13 12 11 00b 11b
0x07 15
14 0
10
9 8 00000000
7
6
5
4
3
2 00000
1
0
0x08 15 0 0x09 15
14
10
9 001b
8
7 00b
6
5 10b
4
3 1
2
1 010b
0
14
BT_RF_PLL_CTRL3 13 12 11 10 1000000000b BT_RF_TIM_CTRL0 13 12 11 TBD BT_RF_TIM_CTRL1 13 12 11 TBD BT_RF_TIM_CTRL2 13 12 11 TBD BT_RF_TIM_CTRL3 13 12 11 TBD BT_RF_TIM_CTRL4 13 12 11 TBD
9
8
7
6
5 00b
4
3 00b
2
1 0
0 0
0x0A 15
14
10 TBD
9
8
7
6 TBD
5
4
3
2 TBD
1
0
0x0B 15
14
10 TBD
9
8
7
6 TBD
5
4
3
2 TBD
1
0
0x0C 15
14
10 TBD
9
8
7
6 TBD
5
4
3
2 TBD
1
0
0x0D 15
14
10 TBD
9
8
7
6 TBD
5
4
3
2 TBD
1
0
0x0E 15
14
10 TBD
9
8
7
6 TBD
5
4
3
2 TBD
1
0
0x0F 15 14 TBD
BT_RF_TIM_CTRL5 13 12 11 10 TBD TBD
9
8 TBD
7
6 TBD
5
4 TBD
3
2
1 TBD
0
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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0x10 15 0 0x11 15 1 PVN
14
BT_RF_AUX_CTRL0 13 12 11 01b 0 BT_RF_AUX_CTRL1 13 12 11 000b
10 9 1000b
8
7 1
6 1
5
4
3 2 000000b
1
0
14
10
9
8
7
6
5
4 0
PVL
01b 01b 1 0 0 Pre power amp output power detection enable 0 : disable 1 : enable Pre power amp power detector reference level 000b(-7dBm), 001b(-5dBm), 010b(-3dBm), 011b(-1dBm) 100b(0dBm), 101b(1dBm), 110b(2dBm), 111b(3dBm)
3 PVN 0
2
1 PVL 100b
0
0x12 15 PVO
14 PVO
BT_RSSI_STA 13 12 RSSI_PO3
RSSI_AGC 0x13 15
6 5 4 RSSI_RF 1 : The current power of pre power amp is more than PVL 0 : The current power of pre power amp is less than PVL AGC gain value with 3dB step from -3dB(0000b) to 42dB(1111b)
11
10
9
8
7
3
2 1 RSSI_AGC
0
14
BT_POW_STA 13 12 11
10
9
8
7
6
5 CSS
4
3
2
1
0
0x14 15
14
BT_DAC_TEST_CTRL 13 12 11 DE 0 BT_PWD_CTRL0 13 12 11
10
9
8 DACI 000000b
7
6
5
4
3
2 DACQ 000000b
1
0
0x15 15
14
10
9
8
7
6 5 PWD_START 10000010b
4
3
2
1 AFS 1
0 DSS 1
0x16 15
14
BT_PWD_CTRL1 13 12 11 PBD 0 BT_ PWDN 13 12
10 9 PWR_TH3 1010b
8
7
6 5 PWR_TH2 0100b
4
3
2 1 PWR_TH1 0110b
0
0x1E 15
14
11
10
9
8
7
6
5
4
3
2
1
0 PD 0
PD
1 : Power down mode enable 0 : Power down mode disable IDCODE 29 28
0x1F 31
30
27
26
25
15
14
13
12
11
10
9
24 23 IDCODE[31:16] 0x0000 8 7
22
21
20
19
18
17
16
6
5
4
3
2
1
0
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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JTAG Registers Programming Timing Diagram in Unidirectional Interface Figure 17. Serial register write programming timing diagram in JTAG
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
22
23
....
28
29
30
31
TCK TMS TDI TDO
High-Z A0 a0 A1 a1 A2 a2 A3 a3 A4 a4 H a5 Don't care D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 D9 Q9 .... D14 D15 .... Q14 Q15 Update register value of Phy
Figure 18. Serial register read programming timing diagram in JTAG
0 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
23
.....
29
30
31
32
TCK TMS TDI TDO
High-Z A0 a0 A1 a1 A2 a2 A3 a3 A4 a4 H a5 Don't care X Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 ..... Q14 Q15 Q9 ..... Q15 X
Update register value of BB
DBUS Registers Programming Timing Diagram in Bidirectional interface Figure 19. Serial register write programming timing diagram in DBUS
0 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
DBCLK BnDEN BDDATA
A7 A6 A5 R A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
BB drives SBDT line Device Address[2:0] Register Address[4:0]
BB drives SBDT line D[15:0] Update register value of Phy
Figure 20. Serial register write programming timing diagram in DBUS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
DBCLK BnDEN
W
BDDATA
A7
A6
A5
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BB drives SBDT line Device Address[2:0] Register Address[4:0]
Phy drives SBDT line D[15:0] Update register value of BB
turn-round point, that is both of BB and Phy don't drive SBDT line
*A7, A6, A5 should be " 101" since it is allocated RF device address in BlueRF standard.
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Electrical specifications
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
Parameter Power Supply Supply Voltage All except IO_VCC (to GND) Supply Voltage IO_VCC (to GND) Input Voltage (All Input Pins) Power Output Short Circuit Duration Continuous Power Dissipation Temperature Operating Temperature Range Storage Temperature Range Lead Temperature(Soldering, 10 sec) TSTG -40 -65 85 150 300 C C C CONT. Condition Symbol Min Typ Max Unit
VDD VPP VI
-0.5 -0.5 -0.5
5 5 VDD+0.5
V V V
Recommended Operating Conditions
Parameter Ambient Temperature Supply Voltage Except IO_VCC (To GND) Supply Voltage IO_VCC (To GND) Condition VDD = 2.7V +/- 5% TA= +25 C TA= +25 C Symbol TA VDD VPP Min -40 Typ 25 2.7 3.3 Max 105 Unit C V V
DC Specifications
Unless otherwise noted, the specification applies for VDD = 2.7V, TA= +25 OC
Parameter Digital Inputs Logical input High
Logical input Low Input capacitance Input leakage current 0.5 < VIN < VPP-0.5 ILEAK VOH VOL VPP-0.4 VPP 0 0.4 10 ISLEEP IIDLE IVCO ITX IRX 30 2.1 10 40 45
Condition
Symbol
VIH VIL
Min
0.8VPP -0.3
Typ
Max
VPP+0.3 0.2VPP
Unit
V V pF A V V pF A mA mA mA mA
3 5
Digital Outputs
Logical output High Logical output Low Output capacitance
Current Consumption
Sleep state Idle state VCO active state TX active state RX active state
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Frequency Synthesizer Specifications
Parameter Lock time Condition fCLK=13MHz fCLK=16MHz Symbol Min Typ 80 80 Max Unit s s
Receiver Specifications
Parameter Cascade Noise Figure Condition LNA + Mixer: max gain BB AGC: max gain LNA + Mixer: max gain BB AGC: min gain LNA + Mixer: min gain BB AGC: max gain LNA + Mixer: min gain BB AGC: min gain LNA + Mixer: max gain LNA + Mixer: min gain No frequency offset 100KHz frequency offset 0.1% BER 0.1% BER 0.1% BER 0.1% BER 0.1% BER 0.1% BER Symbol Min Typ 10 13 27 30 -17 1 -90 -88 2 18 8 -6 -39 -46 20 Max Unit dB dB dB dB dBm dBm dBm dBm dBm dB dB dB dB dB s
Cascade Input 3rd Order Intercept Point (@ LNA + Mixer output) Sensitivity
Maximum receivable signal level C/IAWGN C/Ico-channel C/I@1MHz C/I@2MHz C/I3MHz Receiver turn-on time
Transmitter Specifications
Parameter
Modulation index Maximum frequency deviation Minimum frequency deviation Transmit power Power density at 500KHz offset Adjacent channel (@2MHz) power Adjacent channel (3MHz) power Transmitter turn-on time Maximum transmit power Maximum transmit power Maximum transmit power Transmitting repetitive 00001111 Transmitting repetitive 01
Condition
Symbol
Min
Typ
0.32 160 120 2
Max
Unit
kHz kHz dBm dBc dBm dBm s
25
-47
-53 8
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Application Note
Figure 20. Low cost digital data link using high speed MCU
C1 12p C7 L6 10n 47p 1p C5 L3 10n C4 1p L2 +2.7V 20n C1 L1 +2.7V 10n C5 8 DIG-VCC 15 IO-VCC AN-VCC AN-VCC 24 AN-VCC 25 AN-VCC 100p 26 VCO-VCC 27 VCO-VCC 31 VCO-VCC 32 VCO-VCC L1 20n 100p 34 39 3 4 5 6 7 30 38 33 L5 10n 37 XIAL1 16M C2 12p
23
RF-IN
XTALOUT
XTALIN
22
C6
L4 10n
RF-OUT RF-CNI TEST-P1 TEST-P2 TEST-P3 TEST-P4 TEST-P5 TEST-P6 RF-VCC RF-VCC
47P
TXDATA RXDATA TXACTIVE RXACTIVE TXDATA-EN DATACLK TCLK TMS TDI TDO
12 11 9 10 13 14 17 20 19 18 21 40 41 3.0V
MCU
SYNCDETECT MDSEL GND
1 2
+3.0V C2 C3 10n
R1 10 C3 100P
R2 10 C4 100P
R3 10 C6 1n
R4 10 C7 1n
10n
+2.7V
Figure 21. Bi-directional data link using Base Band Controller PT8R1202
13/16MHz 100pF
XTALO UT
Antenna Filter
RF_IN
Switch
RF_OUT
MDSEL
TXACTIVE RXACTIVE TXDATA_EN TXDATA RXDATA SYNCDETECT DATACLK RESET TCK TMS TDI TDO
XTALIN
TXACTIVE(GPA0) RXACTIVE(GPA1) TXDATA(GPA3) SYNCDETECT(GPA5) DATACLK(GPA6) RFRESET(GPA7) BLUERF_TCK(GPA8) BLUERF_TMS(GPA9) BLUERF_TDO(GPA11)
PT8R1002
PT0124(12/04)
PT8R1202
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XTALIN
Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Mechanical Information
Figure 22. 40-pin Quad Flat Non-lead Package
PT0124(12/04)
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Preliminary Data Sheet PT8R1002 CMOS Zero-IF Radio Transceiver IC for Bluetooth
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Notes
Pericom Technology Inc.
Email: support@pti.com.cn China: Asia Pacific: U.S.A.: Web Site: www.pti.com.cn, www.pti-ic.com No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 3545 North First Street, San Jose, California 95134, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0124(12/04)
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